AN1090 - NoBL™: The Fast SRAM Architecture | Cypress Semiconductor

AN1090 - NoBL™: The Fast SRAM Architecture

최신 업데이트:

2021년 3월 03일

버전:

Processors in high-performance communication equipments and networking applications demand highspeed memories. The type of memory required is determined by the system architecture, the application, and the processor used. System performance suffers if the memory sub-system cannot satisfy the processor requirements.

This application note describes the Cypress NoBL SRAMs architecture designed to improve memory sub-system performance.

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Dear valued customer,

Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you.

Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.

For the full version of this message, please download the PDF version.

번역 문서는 참고용으로만 제공하는 것입니다. 설계 과정에 참여할 경우에는 영어 버전 문서를 참고하는 것이 좋습니다.

파일 제목	언어	Size	최신 업데이트
AN1090 NoBL The Fast SRAM Architecture.pdf	영어	605.62 KB	2021/02/28
AN1090 NoBL The Fast SRAM Architecture (Chinese).pdf	중국어	709.43 KB	2015/08/20
AN1090 NoBL The Fast SRAM Architecture (Japanese).pdf	일본어	794.53 KB	2015/08/20

관련 리소스

데이터시트
CY7C1470V33, CY7C1472V33, CY7C1474V33: 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture	2020/06/09
CY7C1471V25: 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture	2016/11/21
CY7C1471V33: 72-Mbit (2 M × 36) Flow-through SRAM with NoBL™ Architecture	2018/02/15
CY7C1470V25, CY7C1472V25, CY7C1474V25: 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture	2020/06/09
CY7C1461AV33, CY7C1463AV33: 36-Mbit (1 M × 36/2 M × 18) Flow-Through SRAM with NoBL™ Architecture	2020/06/09
CY7C1351G: 4-Mbit (128 K × 36) Flow-through SRAM with NoBL™ Architecture	2020/06/09
CY7C1353G: 4-Mbit (256 K × 18) Flow-Through SRAM with NoBL™ Architecture	2020/06/09
CY7C1352G: 4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture	2016/11/21
CY7C1350G: 4-Mbit (128 K × 36) Pipelined SRAM with NoBL™ Architecture	2020/06/08
CY7C1354CV25, CY7C1356CV25: 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture	2020/06/08
CY7C1355C, CY7C1357C: 9-Mbit (256 K × 36 / 512 K × 18) Flow-Through SRAM with NoBL™ Architecture	2020/06/08
CY7C1354C, CY7C1356C: 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL Architecture	2018/04/09
CY7C1470BV25, CY7C1472BV25: 72-Mbit (2 M × 36/4 M × 18) Pipelined SRAM with NoBL™ Architecture	2018/02/15
CY7C1470BV33, CY7C1472BV33, CY7C1474BV33: 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture	2018/02/15
CY7C1471BV25: 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL Architecture	2016/05/19
CY7C1471BV33, CY7C1473BV33: 72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture	2018/01/29
CY7C1380DV33/CY7C1382DV33, 18-MBIT (512 K X 36/1 M X 18) PIPELINED SRAM	2016/01/05
CY7C1460BV25, CY7C1462BV25: 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture	2016/01/06
CY7C1371DV33: 18-Mbit (512 K × 36) Flow-Through SRAM with NoBL™ Architecture	2016/03/11
CY7C1463BV33: 36-Mbit (2 M × 18) Flow-Through SRAM with NoBL™ Architecture	2016/01/11
CY7C1354D: 9-Mbit (256 K × 36) Pipelined SRAM with NoBL™ Architecture	2020/05/30