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Clock Function (PDL_CLK) | Cypress Semiconductor

Clock Function (PDL_CLK)

최신 업데이트: 
2018년 2월 27일
  • Select the system clock (Master) source
  • Set up external oscillators for main clock (CLKMO) and sub clock (CLKSO)
  • Oscillator stabilization checking and interrupt callbacks
  • Enable/disable PLL clock (CLKPLL) and set K, M and N values
  • Enable/disable APB clocks (PCLKn) and apply dividers
기호 도식
Clock_Function_Symbol Diagram

일반적인 설명

The CLK Component enables firmware control over the internal clocks in the device. It automatically includes the required Peripheral Driver Library (PDL) module and generates data structures required to use the CLK API functions.

Initial clock setup occurs in the Design-Wide Resources Clock Editor. Those settings are applied to the system prior to calling main(). The CLK component allows you to make adjustments to the clocking system from firmware.

CLK Component Parameter Editor

CLK Component Parameter Editor