필터 | Cypress Semiconductor

필터

최신 업데이트: 
2018년 11월 20일
버전: 
2.30
특징

 
  • Easy filter configuration using the Digital Filter Block (DFB) available in select PSoC 3 and PSoC 5 LP devices
  • 별도 필터 채널 2개를 지원하는데, 개별 필터는 최대 4단 설계 단계로 구성됩니다.
  • Multiple FIR and IIR (Biquad) filter methods
  • Support for flexible coefficient entry
  • Final coefficient values available for further analysis
기호 도식

Filter 1 Image

일반적인 설명

The Filter component allows easy creation of single or dual channel digital filters using the DFB. The component includes a filter design feature, which greatly simplifies the design and implementation processes. It supports two streaming channels that can be streamed directly from other hardware blocks (such as the ADC) using DMA. The filtered results can likewise be transferred using DMA, interrupts, or polling methods. The DFB’s 128 data and coefficient locations are shared as needed between the two filter channels, and this information is used to guide the choice of filter implementation. It reports (but does not set) the minimum bus clock frequency required to execute the filtering within the declared sample interval. This clock can then be set in the design-wide resource manager.

The Filter component supports many use cases. If something unusual occurs when using it, please report it (with a good description). Either email psoc_creator_feedback@cypress.com or contact tech support at https://www.cypress.com.



PSoC® Creator 필터 2.0 컴포넌트 동영상

 

 
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