Easy filter configuration using the Digital Filter Block (DFB) available in select PSoC 3 and PSoC 5 LP devices
별도 필터 채널 2개를 지원하는데, 개별 필터는 최대 4단 설계 단계로 구성됩니다.
Multiple FIR and IIR (Biquad) filter methods
Support for flexible coefficient entry
Final coefficient values available for further analysis
The Filter component allows easy creation of single or dual channel digital filters using the DFB. The component includes a filter design feature, which greatly simplifies the design and implementation processes. It supports two streaming channels that can be streamed directly from other hardware blocks (such as the ADC) using DMA. The filtered results can likewise be transferred using DMA, interrupts, or polling methods. The DFB’s 128 data and coefficient locations are shared as needed between the two filter channels, and this information is used to guide the choice of filter implementation. It reports (but does not set) the minimum bus clock frequency required to execute the filtering within the declared sample interval. This clock can then be set in the design-wide resource manager.