You are here

Timer / Counter (TCPWM_Counter_PDL) | Cypress Semiconductor

Timer / Counter (TCPWM_Counter_PDL)

최신 업데이트: 
2018년 3월 26일
특징 기호 도식
  • 16- or 32-bit Timer/Counter
  • Programmable Period Register
  • Programmable Compare Register
    • Compare value can be swapped with a buffered compare value on comparison event
  • Input Capture with buffer register
  • Count Up, Count Down, or Count Up and Down Counting Modes
  • 연속 또는 단일 샷 실행 모드
  • Interrupt and Output on Overflow, Underflow, Capture, or Compare
  • Start, Reload, Stop, Capture, and Count Inputs
  • Peripheral Driver Library (PDL) Component (PDL Application Programming Interface (API) only)

TCPWM Counter Image


일반적인 설명

The TCPWM_Counter_PDL Component is a graphical configuration entity built on top of the cy_tcpwm driver available in the PDL. It allows schematic-based connections and hardware configuration as defined by the Component Configure dialog.

The TCPWM_Counter_PDL Component allows rapid configuration of the TCPWM hardware for Timer/Counter functionality. This Component provides a method to measure time intervals or count external events.