You are here

CY23FP12: 200 MHz Field Programmable Zero Delay Buffer | Cypress Semiconductor

CY23FP12: 200 MHz Field Programmable Zero Delay Buffer

최신 업데이트: 
2017년 3월 21일
버전: 
*K

200 MHz Field Programmable Zero Delay Buffer

특징

  • Fully Field-Programmable
    • Input and output dividers
    • Inverting/noninverting outputs
    • Phase-locked loop (PLL) or fanout buffer configu­ration
  • 10 MHz to 200 MHz Operating Range
  • Split 2.5V or 3.3V Outputs
  • Two LVCMOS Reference Inputs
  • Twelve Low Skew Outputs
    • 35 ps typical output-to-output skew (same frequency)
  • 자세한 사항은 pdf를 참조하십시오
     

기능 설명

The CY23FP12 is a high performance fully field-programmable 200 MHz zero delay buffer designed for high speed clock distribution. The integrated PLL is designed for low jitter and optimized for noise rejection. These parameters are critical for reference clock distribution in systems using high performance ASICs and microprocessors.