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CY29352: 2.5 V or 3.3 V, 200 MHz, 11 Output Zero Delay Buffer | Cypress Semiconductor

CY29352: 2.5 V or 3.3 V, 200 MHz, 11 Output Zero Delay Buffer

최신 업데이트: 
2020년 6월 08일
버전: 
*F

2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer

특징

  • Output frequency range: 16.67 MHz to 200 MHz
  • Input frequency range: 16.67 MHz to 200 MHz
  • 2.5V 또는 3.3V 작동
  • Split 2.5V and 3.3V outputs
  • ±2% maximum output duty cycle variation
  • 11 clock outputs: drive up to 22 clock lines
  • LVCMOS reference clock input
  • 125 ps maximum output-output skew
  • PLL bypass mode
  • 자세한 사항은 pdf를 참조하십시오
     

Description

The CY29352 is a low voltage high performance 200 MHz PLL based zero delay buffer designed for high speed clock distribution applications.

The CY29352 features an LVCMOS reference clock input and provides 11 outputs partitioned in three banks of five, four, and two outputs.