CY7C1268XV18, CY7C1270XV18: 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) | Cypress Semiconductor
CY7C1268XV18, CY7C1270XV18: 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
- 36-Mbit density (2 M × 18, 1 M × 36)
- 633 MHz clock for high bandwidth
- Two-word burst for reducing address bus frequency
- Double data rate (DDR) interfaces (data transferred at 1266 MHz) at 633 MHz
- Available in 2.5 clock cycle latency
- Two input clocks (K and K) for precise DDR timing
- Echo clocks (CQ and CQ) simplify data capture in high speed systems
- Data valid pin (QVLD) to indicate valid data on the output
- Synchronous internally self-timed writes
- DDR II+ Xtreme operates with 2.5 cycle read latency when DOFF is asserted HIGH
- Operates similar to DDR I device with 1 cycle read latency when DOFF is asserted LOW
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The CY7C1268XV18, and CY7C1270XV18 are 1.8 V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 18-bit words (CY7C1268XV18), or 36-bit words (CY7C1270XV18) that burst sequentially into or out of the device.
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