CY7C1329H: 2-Mbit (64K x 32) Pipelined Sync SRAM

2-Mbit (64K x 32) Pipelined Sync SRAM

특징

• Registered inputs and outputs for pipelined operation
• 64K × 32 common I/O architecture
• 3.3V core power supply
• 2.5V/3.3V I/O operation
• Fast clock-to-output times
  • 4.0 ns (for 133-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in JEDEC-standard lead-free 100-pin TQFP package
• “ZZ” Sleep Mode Option
   

기능 설명

The CY7C1329H SRAM integrates 64 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:D] and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.