CY7C1329H: 2-Mbit (64K x 32) Pipelined Sync SRAM | Cypress Semiconductor
CY7C1329H: 2-Mbit (64K x 32) Pipelined Sync SRAM
최신 업데이트:
2018년 1월 31일
버전:
*J
2-Mbit (64K x 32) Pipelined Sync SRAM
특징
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Registered inputs and outputs for pipelined operation
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64K × 32 common I/O architecture
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3.3V core power supply
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2.5V/3.3V I/O operation
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Fast clock-to-output times
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4.0 ns (for 133-MHz device)
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Provide high-performance 3-1-1-1 access rate
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User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
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Separate processor and controller address strobes
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Synchronous self-timed write
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Asynchronous output enable
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Offered in JEDEC-standard lead-free 100-pin TQFP package
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“ZZ” Sleep Mode Option
기능 설명
The CY7C1329H SRAM integrates 64 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:D] and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.