CY7C1345G: 4-Mbit (128 K × 36) Flow-Through Sync SRAM | Cypress Semiconductor
CY7C1345G: 4-Mbit (128 K × 36) Flow-Through Sync SRAM
최신 업데이트:
2016년 11월 21일
버전:
*P
4-Mbit (128 K × 36) Flow-Through Sync SRAM
특징
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128 K × 36 common I/O
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3.3 V core power supply (VDD)
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2.5 V or 3.3 V I/O supply (VDDQ)
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Fast clock-to-output times
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8.0 ns (100 MHz version)
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Provide high performance 2-1-1-1 access rate
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User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences
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Separate processor and controller address strobes
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Synchronous self timed write
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Asynchronous output enable
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Available in Pb-free 100-pin TQFP package
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ZZ sleep mode option
기능 설명
The CY7C1345G is a 128 K × 36 synchronous cache RAM designed to interface with high speed microprocessors with minimum glue logic. The maximum access delay from clock rise is 8.0 ns (100 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK).