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CY7C1352G: 4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture | Cypress Semiconductor

CY7C1352G: 4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture

최신 업데이트: 
2016년 11월 21일
버전: 
*O

4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture

특징

  • Pin compatible and functionally equivalent to ZBT™ devices
  • Internally self-timed output buffer control to eliminate the need to use OE
  • Byte write capability
  • 256 K × 18 common I/O architecture
  • 3.3 V core power supply (VDD)
  • 2.5 V/3.3 V I/O power supply (VDDQ)
  • Fast clock-to-output times
    • 4.0 ns (for 133-MHz device)
  • Clock enable (CEN) pin to suspend operation
  • 자세한 사항은 pdf를 참조하십시오

기능 설명

The CY7C1352G is a 3.3 V, 256 K × 18 synchronous-pipelined burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1352G is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent write/read transitions.

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