CY7C1354D: 9-Mbit (256 K × 36) Pipelined SRAM with NoBL™ Architecture

9-Mbit (256 K × 36) Pipelined SRAM with NoBL™ Architecture

특징

• Pin-compatible and functionally equivalent to ZBT
• Supports 200 MHz bus operations with zero wait states
  
  • Available speed grade is 200 MHz
• Internally self-timed output buffer control to eliminate the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte write capability
• Single 3.3 V power supply (V_DD)
• 3.3 V or 2.5 V I/O power supply (V_DDQ)
• Fast clock-to-output times
  
  • 3.2 ns (for 200 MHz device)
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기능 설명

The CY7C1354D are 3.3 V, 256 K × 36 synchronous pipelined burst SRAM with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1354D are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle.