CY7C1384D: 18-Mbit (512 K × 32) Pipelined SRAM | Cypress Semiconductor
CY7C1384D: 18-Mbit (512 K × 32) Pipelined SRAM
최신 업데이트:
2016년 1월 08일
버전:
*C
18-Mbit (512 K × 32) Pipelined SRAM
특징
- Supports bus operation up to 166 MHz
- Available speed grades are 166 MHz
- Registered inputs and outputs for pipelined operation
- 3.3 V core power supply
- 2.5 V or 3.3 V I/O power supply
- Fast clock-to-output times
- Provides high performance 3-1-1-1 access rate
- 자세한 사항은 pdf를 참조하십시오
기능 설명
The CY7C1384D SRAM integrates 524,288 × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).