CY7C1460BV25, CY7C1462BV25: 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture

36-Mbit (2 M × 18) Pipelined SRAM with NoBL™ Architecture
 

• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
• Internally self-timed output buffer control to eliminate the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte Write capability
• 2.5 V core power supply
• 2.5 V I/O power supply
• Fast clock-to-output times
• Clock enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• For more, see pdf.

기능 설명

The CY7C1460BV25/CY7C1462BV25 are 2.5 V, 1 M × 36/2 M × 18 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™ logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1460BV25/CY7C1462BV25 are equipped with the advanced NoBL logic required to enable consecutive read/write operations with data being transferred on every clock cycle.