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CY7C1470BV25, CY7C1472BV25: 72-Mbit (2 M × 36/4 M × 18) Pipelined SRAM with NoBL™ Architecture | Cypress Semiconductor

CY7C1470BV25, CY7C1472BV25: 72-Mbit (2 M × 36/4 M × 18) Pipelined SRAM with NoBL™ Architecture

최신 업데이트: 
2018년 2월 15일
버전: 
*O

72-Mbit (2M x 36/4M x 18) Pipelined SRAM with NoBL™ Architecture

특징

  • Pin-compatible and functionally equivalent to ZBT™
  • Supports 250 MHz bus operations with zero wait states
    • Available speed grades are 250, 200, and 167 MHz
  • Internally self-timed output buffer control to eliminate the need to use asynchronous OE
  • Fully registered (inputs and outputs) for pipelined operation
  • Byte Write capability
  • Single 2.5V power supply
  • 2.5V I/O supply (VDDQ)
  • Fast clock-to-output times
  • 자세한 사항은 pdf를 참조하십시오

기능 설명

The CY7C1470BV25 and CY7C1472BV25 are 2.5 V, 2 M × 36/4 M × 18 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read or write operations with no wait states. The CY7C1470BV25 and CY7C1472BV25 are equipped with the advanced (NoBL) logic required to enable consecutive read or write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent read or write transitions. The CY7C1470BV25 and CY7C1472BV25 are pin-compatible and functionally equivalent to ZBT devices.