CY7C1470V33, CY7C1472V33, CY7C1474V33: 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture

72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture

특징

• Pin compatible and functionally equivalent to ZBT
• Supports 200 MHz Bus operations with zero wait states
  • Available speed grades are 200 and 167 MHz
• Internally self timed output buffer control to eliminate the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte write capability
• Single 3.3 V power supply
• 3.3 V/2.5 V I/O power supply
• Fast clock-to-output time
• 자세한 사항은 pdf를 참조하십시오

기능 설명

The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are 3.3 V, 2 M × 36/4 M × 18/1 M × 72 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™ logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent write/read transitions. The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are pin compatible and functionally equivalent to ZBT devices.