CY7C1471BV25: 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL Architecture | Cypress Semiconductor
CY7C1471BV25: 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL Architecture
72-Mbit (2 M × 36/1 M × 72) Flow-Through SRAM with NoBL™ Architecture
No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
Supports up to 133 MHz bus operations with zero wait states
Data transfers on every clock
Pin compatible and functionally equivalent to ZBT™ devices
Internally self timed output buffer control to eliminate the need to use OE
Registered inputs for flow through operation
Byte Write capability
2.5 V IO supply (VDDQ)
Fast clock-to-output times
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The CY7C1471BV25, and CY7C1475BV25 are 2.5 V, 2 M × 36/1 M × 72 synchronous flow through burst SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states. The CY7C1471BV25, and CY7C1475BV25 are equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read or write operations with data transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.
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