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CY7C1471V25: 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture | Cypress Semiconductor

CY7C1471V25: 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture

최신 업데이트: 
2016년 11월 21일
버전: 
*S

72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture

특징

  • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
  • Supports up to 133 MHz bus operations with zero wait states
  • Data is transferred on every clock
  • Pin compatible and functionally equivalent to ZBT™ devices
  • Internally self timed output buffer control to eliminate the need to use OE
  • Registered inputs for flow through operation
  • Byte write capability
  • 2.5 V I/O supply (VDDQ)
  • Fast clock-to-output times
  • 자세한 사항은 pdf를 참조하십시오

기능 설명

The CY7C1471V25 are 2.5 V, 2 M × 36 synchronous flow through burst SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states. The CY7C1471V25 are equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read or write operations with data transferred on every clock cycle.