You are here

CY7C1521KV18, 72-Mbit DDR II SRAM Four-Word Burst Architecture | Cypress Semiconductor

CY7C1521KV18, 72-Mbit DDR II SRAM Four-Word Burst Architecture

최신 업데이트: 
2017년 11월 30일
버전: 
*M

72-Mbit DDR II SRAM Four-Word Burst Architecture

특징
 

  • 72-Mbit Density (2 M × 36)
  • 250 MHz Clock for High Bandwidth
  • 4-word Burst for reducing Address Bus Frequency
  • Double Data Rate (DDR) Interfaces (data transferred at 500 MHz) at 250 MHz
  • Two Input Clocks (K and K) for precise DDR Timing
    • SRAM uses rising edges only
  • Two Input Clocks for Output Data (C and C) to minimize Clock Skew and Flight Time mismatches
  • Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems
  • Synchronous Internally Self-timed Writes
  • For more, see pdf.

기능 설명

The CY7C1521KV18 is 1.8 V Synchronous Pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a two-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided.

번역 문서는 참고용으로만 제공하는 것입니다. 설계 과정에 참여할 경우에는 영어 버전 문서를 참고하는 것이 좋습니다.