CY7C2168KV18, CY7C2170KV18: 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

특징

• 18 Mbit density (1 M x 18, 512 K x 36)
• 550-MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Data valid pin (QVLD) to indicate valid data on the output
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기능 설명

The CY7C2168KV18, and CY7C2170KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock.