CY7C2168KV18, CY7C2170KV18: 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT | Cypress Semiconductor
CY7C2168KV18, CY7C2170KV18: 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
최신 업데이트:
2018년 1월 29일
버전:
*J
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
특징
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18 Mbit density (1 M x 18, 512 K x 36)
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550-MHz clock for high bandwidth
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Two-word burst for reducing address bus frequency
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Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
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Available in 2.5 clock cycle latency
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Two input clocks (K and K) for precise DDR timing
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SRAM uses rising edges only
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Echo clocks (CQ and CQ) simplify data capture in high-speed systems
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Data valid pin (QVLD) to indicate valid data on the output
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기능 설명
The CY7C2168KV18, and CY7C2170KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock.
관련 파일
| 파일 제목 | 언어 | Size | 최신 업데이트 |
|---|---|---|---|
 CY7C2168KV18, CY7C2170KV18: 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
영어 | 868.13 KB | 2018/01/17 |