CY7C25422KV18: 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT | Cypress Semiconductor
CY7C25422KV18: 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT
72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT
- Separate independent read and write data ports
- 333 MHz clock for high bandwidth
- Two-word burst for reducing address bus frequency
- Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
- Available in 2.0 clock cycle latency
- Two input clocks (K and K) for precise DDR timing
- Echo clocks (CQ and CQ) simplify data capture in high speed systems
- Data valid pin (QVLD) to indicate valid data on the output
- On-Die Termination (ODT) feature
- 자세한 사항은 pdf를 참조하십시오
The CY7C25422KV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR® II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common devices.
Dear valued customer,
Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you.
Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.
For the full version of this message, please download the PDF version.