User Module Datasheet: 12-Bit Incremental ADC Datasheet ADCINC12 V 5.3 (CY8C29/27/24/22x13, CY8C23x33, CY8CLED04/08/16, CY8C28x45, CY8C28x43, CY8C28x52, CYWUSB6953) | Cypress Semiconductor
User Module Datasheet: 12-Bit Incremental ADC Datasheet ADCINC12 V 5.3 (CY8C29/27/24/22x13, CY8C23x33, CY8CLED04/08/16, CY8C28x45, CY8C28x43, CY8C28x52, CYWUSB6953)
Features and Overview
12-bit resolution, 2’s complement
Sample rate from 7.8 sps to 480 sps
Input range AGND /- VRef
Provides normal mode rejection of high frequency harmonics
Internal or external clock
The ADCINC12 User Module implements a 12-bit incremental A/D that generates a 12-bit, full-scale 2’s complement output (2047 to -2048 count range) with several input ranges to select from. Input voltage ranges, including rail-to-rail, may be measured by configuring the proper reference voltage and analog ground. It supports sample rates from 7.8 sps to 480 sps. The ADCINC12 programming interface allows you to select from 0 to 255 samples, where zero specifies continuous sampling.
The ADCINC12 is an integrating ADC that provides removal of higher frequencies. Optimum rejection of 50 Hz, 60 Hz, and any harmonics of these two frequencies (normal mode rejection) can be achieved by setting the sample window to 100 ms (sample rate to 9.84 sps). The CPU load varies with the input level.