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Additive Phase Jitter in High Performance Clock Distribution | Cypress Semiconductor

Additive Phase Jitter in High Performance Clock Distribution

최신 업데이트: 
2020년 5월 28일
버전: 
*B

One of the critical parameters in high-end clock distribution is an additive phase jitter. This document outlines what additive phase jitter is and why it is important to consider while selecting devices for the clock signal fanout in a system. A sample additive phase jitter measurement of the Cypress High-Performance Buffer product is also described.