TIMING UNCERTAINTY IN HIGH PERFORMANCE CLOCK DISTRIBUTION | Cypress Semiconductor
TIMING UNCERTAINTY IN HIGH PERFORMANCE CLOCK DISTRIBUTION
Several factors contribute to the timing uncertainty when using fanout buffers to distribute a clock to synchronize various devices within a system. For non-PLL clock fanout buffers, output skew, propagation delay, and edge rates play a critical role in determining system timing margin. This White Paper briefly discusses these parameters and their effect on system performance.