CY8C20234-12LKXI | Cypress Semiconductor
CY8C20234-12LKXI
Development Kit | CY3203A-DK |
인증 자동차 | N |
CPU Core | M8C |
CapSense | Y |
통신 인터페이스 | I2C, SPI |
전용 ADC (No._ 최대 해상도 @ 샘플링 속도) | DelSig (1, 10-bit @ 5.9 ksps) |
Dedicated DAC (No._ Max. Resolution @ Sample Rate) | 없음 |
플래시(KB) | 8 |
LCD Direct Drive | N |
최대 작동 주파수(MHz) | 12 |
최대 작동 온도(°C) | 85 |
최대 작동 전압(V) | 5.25 |
최소 작동 온도(°C) | -40 |
최소 작동 전압(V) | 2.40 |
No. of CapSense Channels | 1 |
CapSense IO 수 | 10 |
No. of Dedicated Comparators | 0 |
No. of Dedicated I2C | 1 |
No. of Dedicated OpAmps | 0 |
No. of Dedicated SPI | 1 |
No. of Dedicated UART | 0 |
GPIO 개수 | 13 |
프로그래밍 가능한 디지털 블록 개수 | 0 |
PWM | SW |
근접 센싱 | N |
SRAM(KB) | 0.5 |
SmartSense 작동 | N |
Tape & Reel | N |
USB (Type) | 없음 |
Pricing & Inventory Availability
1-9 unit Price* | 10-24 unit Price* | 25-99 unit Price* | 100-249 unit Price* | 250-999 unit Price* | 1000+ unit Price* |
---|---|---|---|---|---|
$1.77 | $1.70 | $1.62 | $1.55 | $1.48 | $1.35 |
Packaging/Ordering
패키지
No. of Pins
16
Package Dimensions
118 L x 23 H x 118 W (Mils)
Package Weight
15.57 (mgs)
Package Cross Section Drawing
Package Carrier
TRAY
Package Carrier Drawing / Orientation
Standard Pack Quantity
4900
Minimum Order Quantity (MOQ)
980
Order Increment
980
Estimated Lead Time (days)
182
HTS Code
8542.31.0001
ECCN
없음
ECCN Suball
EAR99
Quality and RoHS
Moisture Sensitivity Level (MSL)
3
Peak Reflow Temp. (°C)
260 (Cypress Reflow Profile)
RoHS 준수
무연
Y
Lead/Ball Finish
Ni/Pd/Au/Ag;Pure Sn
Marking
Device Qualification Reports
FIT/MTBF, ESD (HBM/CDM) and Latch-up data available in the Device Qualification Report.
기술 문서
기술 참조 설명서(1)
애플리케이션 설명 (18)
2020년 6월 26일
개발 키트/보드 (1)
소프트웨어와 드라이버 (2)
제품 변경 고지(PCN) (10)
2018년 5월 28일
Qualification of Grace Semiconductor as an alternate wafer fabrication site for the PSoC CY8C20xx4 product family
2018년 5월 27일
Standardization of Moisture Sensitive Level (MSL) Classification for 16-Lead QFN Pb - Free package assembled in Amkor-Phil
2017년 10월 24일
Qualification of Cypress Minnesota Inc. as an alternative wafer fabrication site and Copper Palladium as an alternative wire bond option for select PSoC Capsense Controller Product families
2017년 10월 23일
Qualification of ASE Taiwan as an additional assembly site for all Quad Flat No-Lead (QFN) packaged products
Product Information Notice (PIN) (6)
2020년 4월 14일
Addendum to PIN195102 - Manufacturing Label and Packing Configuration Standardization
2017년 11월 07일
Qualification of Test 25 (Austin, Texas) as an Additional Wafer-Level Test Location.
2017년 11월 06일
GSMC Merger with HH-NEC to Form HHGrace Semiconductor Manufacturing Corporation