For 35 year Cypress has been developing industry leading memory products to meet the latest customer and market needs. While our roadmap demonstrates a continued commitment to innovation and long-term support, we still offer memory products that were industry leading on one time. We still have loyal customers who love these products for long running systems but we do not recommend them for new designs. However, if you would like, we would be happy to supply them to you.
The QDR consortium defined QDR (Quadruple Data Rate) SRAM products are geared primarily to the networking and communication market. The QDR SRAMs are similar to NoBL SRAMs but with architectural enhancements such as double data rate I/Os, and dedicated read write ports. The QDR SRAMs are used in networking applications where reads and writes are balanced such as packet buffer, statistics counters, flow state, and scheduling. The QDR SRAMs have a maximum clock speed of 167MHz with a read latency of 1 cycle and are available in an industry standard 165 Ball BGA.
The QDR consortium defined DDR CIO SRAMs are similar to the legacy Synchronous Burst SRAM products but with double data rate I/Os. Like the Synchronous Burst SRAMs they are used for read intensive functions such as packet look up and packet classification in networking/communication applications. The DDR SRAMs have a maximum clock speed of 167MHz with a read latency of 1 cycle and are available in an industry standard 165 Ball BGA
The DDRII SRAMs are similar to DDR SRAMs in their operation but with some performance improvements. The DDRII SRAMs include source synchronous free running echo clocks (CQ, /CQ) that enable customers to easily capture data. The DDRII SRAMs also support 1.5V HSTL interface. The applications are the same as that of DDR SRAMs. The DDRII SRAMs have a maximum speed of 333MHz with a read latency of 1.5 cycles, with burst lengths of 2 and 4, and are available in an industry standard 165 Ball BGA.
The DDRII SIO SRAMs are similar to DDRII CIO SRAMs but they include two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operation and the write port has data inputs to support write operation. The DDR II SIO SRAM completely eliminates the need to "turnaround" the data bus required with common I/O devices.
The DDRII+ SRAMS are similar to DDRII+ SRAMs in their operation but with additional performance improvements. The redundant data input clocks (C & /C) are not present in the DDRII+ suite of products. Instead DDRII SRAMs include a hand shake signal (QVLD) that indicates when the Data will become valid thereby simplifying data capture. The customers also have the choice of QDRII products with programmable ODT (On Die Termination). The ODT feature turns on during a write cycle and turns off during a read cycle to save power. The DDRII+ SRAMs have a maximum speed of 550MHz with read latencies of either 2 cycles or 2.5 cycles, with a burst length of 2 and are available in an industry standard 165 Ball BGA.
Cypress의 고속 동기식 SRAM에는 표준 동기식 파이프라인형, NoBL™(No Bus Latency™), QDR™(Quad Data Rate™), DDR(Double Data Rate) SRAM이 포함되며 일반적으로 네트워킹 애플리케이션에서 사용됩니다. Cypress 동기식 SRAM은 코드 체계표, 링크 목록, 큐 관리, 트래픽 조정(Policing) 및 패킷 버퍼에 이상적인 솔루션입니다. Cypress 동기식 SRAM 포트폴리오는 다양한 속도, 버스 폭, 밀도 및 패키지의 수 백여 개의 메모리로 구성됩니다. 산업 표준 핀 아웃을 사용하는 Cypress 동기식 SRAM 제품은 최신 설계와 기존 설계 모두에 쉽게 통합됩니다.
듀얼 포트 SRAM
Cypress is a market leader in multi-port memory solutions, offering highest performance interconnects solutions in the industry. Cypress offers a wide Product portfolio of more than 300 types of Asynchronous and Synchronous Dual Ports, Quad Ports and FullFlex Dual Ports.
MoBL 듀얼 포트
Cypress offers a variety of high performance and low power Inter-Processor Communication (IPC) solutions. These interconnects allow IPC between multiple processors in various applications. Our MoBL® family of Dual-Ports is specially optimized for consumer and handheld devices.